Cryptocurrency mining is painstaking, expensive, and only intermittently rewarding. Bitcoin mining is the process by which transactions are established and added to the public ledger, known as the blockchain. With access to the internet and suitable hardware such as ASIC’s one can participate in the mining process. The mining process involves assembling recent transactions into blocks and trying to solve a computationally complicated puzzle The member who first solves the puzzle gets to position the next block on the blockchain and claims the rewards. The rewards, which stimulate mining, include both the transaction fees associated with the transactions compiled in the block as well as newly released Bitcoin.
Process of Mining
The difficulty of the mining process is adjustable and is done by the protocol every 2016 blocks, or roughly every 2 weeks. The difficulty rearranges itself with the aim of keeping the rate of block discovery constant. When more computational power is employed in mining, then the difficulty will regulate upwards to make mining harder while when computational power is taken off of the network, the opposite happens. The difficulty adjusts downward to ease mining.
The process of Bitcoin mining creates blockchain that verifies Bitcoin transactions and also generates new Bitcoins. The block reward is gleaned by placing a new block on the blockchain, which acts as an advancing public ledger of a verified transaction. This is an essential function of Bitcoin’s operation as it enables the currency to be safely and predictably created without the centralized regulation in the form of a bank or federal government. Blocks must be validated by a proof-of-work (Bitcoin uses Hashcash), which can only be obtained by expanding a great deal of processing power. Once a block is obtained a message is broadcasted to the mining network and verified by all recipients.
Bitcoin mining can still be fun and even profitable if you have cheap electricity and an efficient Bitcoin mining hardware. All serious Bitcoin mining process is performed on dedicated Bitcoin mining hardware ASICs, usually in thermally-regulated data-centres with access to low-cost electricity.
Factors to consider before before purchasing Bitcoin Mining ASIC
There are some important factors to be considered while determining which Bitcoin mining ASIC to purchase:
Hash rate – How many hashes per second are generated through Bitcoin miner? Production of more hashes will cost more, thus establishing efficiency cruciality.
Efficiency – The miner with higher efficiency needs to be considered. Since miners consume a huge amount of electricity, one should prefer that converts the most amount of electricity into Bitcoins.
Price – The cost of the mining hardware along with its efficiency and electricity usage is an essential factor to be considered. Cheap mining hardware will mine fewer Bitcoins and their electricity consumption will be more as compared to one that costs more.
What are ASICS?
An application-specific integrated circuit (ASIC) is an integrated circuit that is specially built for a unique application or purpose. ASIC is designed to improve speed.It can also be made smaller to use less electricity. An ASIC can be found in almost any electronic device and its utility can range from custom rendering of images to sound conversion. They are arguably a driving force behind the centralization of computing power on cryptocurrency networks.
There are three different categories of ASICS:
- Full-Custom ASICS: These are custom-made for a specific application from scratch. Their ultimate purpose is set by the designer. All the photolithographic layers of this integrated circuit are fully predefined, leaving no option for modification during manufacturing.
- Semi-Custom ASICs: These are fractionally customized to perform different functions within the field of their intended area of application. These ASICS are designed to enable some modification at time of manufacture, although the masks for the diffused layers are already fully defined.
- Platform ASICs: These are designed and produced on a defined set of methodologies, intellectual properties and a well-defined design of silicon that shortens the design cycle and reduces development costs. Platform ASICs are developed from predefined platform slices, where each slice is a pre-manufactured device, platform logic or entire system. The use of pre-manufactured materials minimizes the development costs for these circuits.
Reasons to use ASICs
An ASIC is obviously smaller than few interconnected standard products on a PC board. Having a variability in size enables the chip to be small or large as necessary. This reason alone is why many electronics have reduced in their size.
Power and Performance
ASIC devices utilizes less electrical power as compared to a collection of standard components due to their small size. In addition, an ASIC consists of only the circuitry required for the application. So the chip is much more efficient due to the miniature size and power requirements.
ASIC chips provide you with IP protection as it’s specifically designed for the user. This creates a high barrier to entry and also easy differentiation between a user and the competition.
A high initial investment is coupled with high payoff. A product using an ASIC needs fewer electronic components and is cheaper to assemble. Having fewer parts translates into higher reliability overall.
Smarter, Faster, More Reliable
An ASIC is a smart choice for varying reasons. An ASIC can miniaturize product’s size, costs can be considerably reduced and one gets a chip specific for the user and non-accessible by others. These reasons alone should give you sufficient incentive to consider the development of your own ASIC.
The M10 presents itself as a more robust, cost-effective alternative to otherwise highly expensive ASIC mining hardware that can be out of the reach of independent miners. It’s easy to disassemble framework means that it is able to reduce the amount of labour time needed in order to properly maintain the hardware, giving it a far better rate of longevity for intensive mining. The Pangolin WhatsMiner M10 provides an overall hash rate of 33 TH/s while also offering a significantly good power to consumption ratio of 65W/T, offering an improved level of efficiency for its hash rate and underlying power consumption.
GMO Miner B3
This new model uses the mining ASIC of the 7nm process GMO72b which supports cryptocurrency mining of SHA256 and can perform mining of Bitcoin and Bitcoin cash. The B3 model operates with a maximum output of 33TH/s will consume 3,417w per unit or 103W per TH/s.
The B3 model contains a newly incorporated function to set the optimal hash power and power consumption depending on the environment. It comprises of daisy chain connection of up to 32 units, an online update of software and online monitoring of the operation status. There are two operational modes to this new function: the automatic mode and the manual mode. The automatic mode adjusts the hash power optimally up to 33TH/s in accordance with the electricity cost. The hash power varies depending on the mining environment, and changes in the indicators such as the global hash rate. This allows mining operators to improve efficiency.
Manufactured by Innosilicon, the T2 is the latest Bitcoin ASIC mining hardware. It is based on 10nm chip technology. The Innosilicon T2 implements SHA-256 algorithm and churns out 24 TH/s with a power consumption of 1980W by utilizing the Samsung Foundry’s low-power Finfet semiconductor technology.
The implementation of new technologies is reflected in the hash rate and power efficiency of the miner. The network connection is based on Ethernet platform with an ambient temperature between 0º C and 85º C.
Antminer S9 Hydro
Antminer S9 Hydro contains a water cooled system, creating a new mining model with low noise and high energy savings. This new miner supports the SHA256 algorithm and a power consumption of 1728W it produces hashrate of 18TH/s and it can mine mainstream digital currencies such as BTC and BCH. Hydro is incorporated with water cooling system for heat dissipation and it can mine along with a specific power source: the APW5. S9 Hydro-Hex external water circulation module for heat dissipation can be used by an individual miner, while in large mining farms, low noise and high energy saving mining effects can be achieved with an outdoor water source.
Antminer S9 Hydro is equipped with the most innovative water cooling design available for heat dissipation. Due to customized and high-precision water cooling module, S9 Hydro can support the direct introduction of an outdoor water source that meets the water quality requirements and enables a quick cooling down of the computing boards and other components inside the miner. At the time of run, the chip temperature difference is only around 5°C, which improves performance and stability of the miner.
Antminer S9 Hydro performance in terms of noise reduction is praiseworthy. The water cooling system reduces both the internal temperature of the miner and noise produced during the operation. Dust proofing and easy maintenance is an advantage. The required air volume of the miner is greatly reduced through water circulation system and it effectively avoids dust deposits inside the machine and decreases the risk of short circuit or corrosion of internal components.
Manufactured by Halong Mining the Dragonmint T16.
Dragonmint T16 consumes 0.075J/GH and boasts 16 TH/s making it powerful.
Its ASICBOOST has an ability to further boosts efficiency by an extra 20%. The DragonMint 16T’s new DM8575 generation of ASIC chips, the 16T has become the most electrically-efficient miner on the market. Consuming merely 0.075J/GH drastically increase the profitability of a mining operation. This hardware is beneficial not only for mining on a large scale but also for individual miner.
Bitmain Antminer S9i
The S9 has hashing power of 14 TH/s (Tera Hash per second). A total of 189 chips, spread over 3 circuit boards, are combined to achieve this phenomenal hash rate. It uses a mere 0.1 Joules per Giga hash. Excluding the power supply component, the S9 is a self-contained unit. It requires no connection to another computer to establish connectivity with other Bitcoin nodes. Its web management portal enables a simplified setup and maintenance process. The S9 is air-cooled and its robust design allows it to be maintained and serviced.
Pangolin Whatsminer M3X
WhatsMiner M3X also referred as MicroBT is a Bitcoin (SHA-256) ASIC miner using 28nm ASIC chip technology, manufactured by Shenzhen Bit Microelectronics Technology Co.
According to the official technical specifications, weighing around 7.15 kg the nominal hashrate is from 12.0 to 13.0 Th/s with a nominal power consumption of 1800-2100 Watts. The power supply unit is called WhatsPower P5 and requires 180-240 V mains voltage for its operation.
WhatsMiner M3X is a standalone miner with a built-in controller board and it doesn’t require a separate controller unit to run it. It has a 28nm ASIC, SMTI 1700 chipset with 2 x Fans for the purpose of cooling. The miner runs at the optimum temperature of -20C – 75C and uses a 2100W customized power supply unit
It’s only ideal for specific people or companies who are ready to make more money faster, have a place to operate as it’s extremely loud and has enough money and ability to constantly supply the miner with power.
Bitmain Antminer R4
Bitmain’s BM1387 chip is built using TSMC’s 16nm FinFET technology and delivering 0.098 J/GH/s. Antminer R4 constitute of 126 such chips to deliver more hashrate and efficiency.
Antminer R4 employs the Xilinx’s ZYNQ-7000 family system-on-a-chip (SoC) that integrates a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) as well as a 28 nm Xilinx programmable logic (PL) in a single device and ropes Gigabit Ethernet to ensure that mined blocks are submitted instantaneously. The R4 manages to deliver a hashrate of 8.6TH/s.
The R4’s design derived a unique solution to do away with the traditional noisy fan.
Inspired by the “fan” of a silent split air conditioner, the fan creates reduced noise level and its speed is automatically controlled to ensure it never creates more noise than is absolutely necessary.
After accessing the Antminer’s user interface, one needs to enter wallet address and mining pool settings, before starting to mine. The user interface also enables user to customize settings such as the fan speed or the frequency and can be upgraded to new versions from Bitmain.
Antminer R4 has Optional Custom-built PSU APW5 for Further Noise Reduction. The APW5 works with both 220V and 110V input to deliver 2600W and 1300W, respectively.
The Avalon 6 contains eighty 18nm A3218 chips, running at 500 MHz to achieve a respectable 3.5 TH/s hash rate with any good power supply of 1100W and up. The ASIC unit further reduces the noise level by underclocking. Either a Raspberry Pi (B / B+) or a TP-Link TL-WR703N can act as a controller in an Avalon 6. It is easy to install because it uses DHCP which automatically detects an IP address.
Through Avalon’s control panel or CGminer the device can be controlled and monitored. Setting up a pool and worker information feature is added to the configuration panel. The dual panel closed tunnel design leaves some room to facilitate cooling down of the unit.
This airflow method allows for a smooth airflow over the heat sinks and boards. The fan control software allows for you to set manually your temperature to fan speed threshold and is very effective.
More advanced users can SSH into the control software and modify the base CGMiner with 3rd party firmware to accept higher frequency. Updating the Avalon firmware is simple as well. The main Avalon control panel can establish direct links to the DL site.
The excellent cooling and power to hash rate ratio while allowing for easy deployment and management makes it a worth investing money.
Bitmain Antminer S7
Bitmain’s AntMiner S7 powered by a 28nm BM1385 ASIC chip offers a hashrate of 1 TH/s and consumes a modest 0.25 Joules of power per Gigahash. These chips 135 in number are spread across 3 boards and are cooled by dual fans. The metal casing with a groove system and a tongue allows miners in numbers to be arranged neatly. The S7 coupled with its own PSU 1000W Enermax with over 80% efficiency. The S7-LN only draws about 700W, and the PSU has excess capacity even when the unit is working above its default 600M frequency. It is best suited to be used with 1600 Watt APW3 power supply. The APW3 needs a minimum of 205 volts to function and sadly does not come with the necessary 16A power cord.
TheS7’s have DHCP capability, meaning they’ll automatically seek out an IP address to use. Setting them up through the MinerLink GUI is a simple process and requires one’s mining pool credentials to begin mining. When supplied with power the hashing begins and its connectivity is upon powering enough Ethernet only. it should be kept in a room with a cool and dry place to ensure its longevity
Advancements In Mining Hardware
Basically, there exist three options through which crypto mining can be performed: CPU, GPU, and ASIC.
CPU(Central Processing Unit) mining is the most primitive form of mining and is least profitable. A good CPU delivers low hashrate and monthly earnings will most likely be in the single digits. Thus, CPU mining is unlikely to be considered an option.
Mining with GPU (Graphics Processing Unit) is a step forward compared to CPU. They are costly and consume lots of electricity. It enables mining on various form of currencies.
ASIC deliver high hashrate with lower electricity consumption compared to two above forms. They are expensive to start with and enables the mining of only single cryptocurrency kind.
What is an FPGA?
Field Programmable Gate Arrays (FPGAs) are fundamentally a semiconductor device that revolves around a matrix of configurable logic blocks (CLBs) associated through programmable interconnects. FPGAs are reprogrammable silicon chips and can be done so for desired application or functionality.
Using prebuilt logic blocks and programmable routing resources, the chips can be configured to implement custom hardware functionality. FPGA chip enactment across all industries is driven by the fact that FPGAs consolidate the best parts of ASICs and processor-based frameworks. Reprogrammable silicon likewise has a similar adaptability of software running on a processor-based framework, yet it isn’t constrained by the number of processing cores available.
Each independent processing errand is assigned to a dedicated section of the chip and can function independently without any impact from other logic blocks. Different processing operations do not have to compete for the same resources as a result, the performance of one part of the application is not affected when more processing is added.
FPGA’s are slower than equivalent ASICs (Application Specific Integrated Circuit) and additionally, they are more expensive. This establishes that the choice of whether to use an FPGA based design should be made early in the design cycle and will depend on such items as whether the chip requires to be re-programmed or equivalent functionality can be obtained elsewhere and certainly the allowable cost. Sometimes manufacturers may opt for an FPGA design for an early product when bugs may still be found, and then use an ASIC when the design is fully stable.
The word Field in the name itself signifies to the capacity of the gate arrays to be customized for a particular function by the client rather than by the manufacturer of the gadget. The word Array signifies a progression of rows and columns of gates that can be programmed by the end client.
FPGAs are pre-assembled silicon chips that can be programmed electrically to execute digital designs
. The FPGA Architecture consists of three major components
Programmable Logic Block
The programmable logic block caters fundamental computational and storage components utilized in digital systems. A basic logic element constitutes of programmable combinational logic, a flip-flop, and some fast carry logic. Modern FPGA’s contains a heterogeneous blend of various blocks like dedicated memory blocks, multiplexers. Configuration memory is used throughout the logic blocks to control the unique function of each component.
The programmable routing authorizes a connection between logic blocks and Input/Output blocks to complete a user-defined design unit. It contains multiplexers pass transistors and tri-state buffers. Pass transistors and multiplexers are utilized in a logic cluster to associate the logic elements.
- I/O blocks used to make off-chip connections
The programmable I/O pads are used to confluence the logic blocks and routing architecture to the external components. I/O cell consume a large portion of the FPGAs area. The design of I/O programmable blocks is complex due to great differences in the supply voltage and reference voltage. With advancement, the basic FPGA Architecture has developed through the addition of more specialized programmable function blocks such as ALUs, block RAM, multiplexers, DSP-48 and microprocessors.
FPGA Architecture Design Flow
FPGA Architecture design comprises of design entry, design synthesis, design implementation, device programming and design verification.
The design entry is executed through different techniques like schematic based, hardware description language (HDL) and a combination of both. Schematic entry is preferred when a designer wants to deal with hardware. When looking at a design in an algorithmic way, HDL is the better choice. The schematic based entry provides the designer a greater visibility and control over the hardware.
This process converts VHDL code into a device netlist format, i.e., a complete circuit with logical elements. The design synthesis process will review the code syntax and analyze the hierarchy of the design architecture. Further, the netlist format is converted and saved as Native Generic Circuit (NGC) file.
The implementation process consists of
- Translate– This process merges complete input netlists to the logic design file saved as NGD (Native Generic Database) file. Here the ports are accredited to the physical elements like pins, switches in the design. This is stored in a file called User Constraints File (UCF)
- Map- Mapping divides the circuit into sub-blocks in a manner that they fit into the FPGA logic blocks. Mapping generates a NCD file which represents the design mapped to the components of FPGA. It does so after sub-blocks fits the logic defined by NGD into the combinational Logic Blocks and Input-Output Blocks,
- Routing- This process puts the sub-blocks from the mapping process into the logic block according to the defined parameters and then connects the logic blocks.
The logic block in an FPGA can be implemented in a variety of ways. The implementation depends upon series of FPGA being used and the manufacturer. The variations include the number of inputs and outputs and the general complexity of the logic block.
Device Programming- The routed design should be loaded into the FPGA. Then the design is converted into a format supported by the FPGA. The routed NCD file is provided to the BITGEN program, which generates the BIT file. This BIT file is then configured to the FPGA.
Design Verification- Design verification consists of functional verification and timing verification that occurs at the time of design flow.
Verification can be done at various stages of the process.
Behavioral Simulation (RTL Simulation)
The first step in the hierarchy of the design is Behavioral simulation. This is performed before cheap lace addresses the synthesis process to verify the RTL code. In this process, the signals and variables are observed and further, the procedures and functions are traced and breakpoints are marked.
Functional simulation is executed post-translation simulation. It conveys information regarding the logical operation of the circuit.
Static Timing Simulation
This is performed post mapping. The signal path delays are indicated by post map timing report. This provides a complete timing summary of the design.
Designing with FPGAs
Considering the complexity of FPGAs, software is used to scheme the function of FPGA. The FPGA design process is initiated by the client after providing a Hardware Description Language (HDL) definition. This step is followed by a step to produce a netlist generated for the particular FPGA family being used. This explains the connectivity needed within the FPGA and is generated through electronics design automation tool. The netlist is then fitted to the actual FPGA architecture using a process called place-and-route, mostly performed by the FPGA company’s proprietary place-and-route software.
Finally the design is committed to the FPGA and used in the electronic circuit board for which it is intended initially.
It is necessary to undertake rigorous testing of the FPGA design due to their complexity. This testing is usually performed at each stage of the FPGA development process. It includes timing analysis, functional simulation and other verification methodologies. After the completion of the design and validation process, the binary file generated (also using the FPGA company’s proprietary software) is utilized to configure the FPGA device
- Performance– Taking advantage of hardware parallelism, FPGAs transcends the computing power of digital signal processors (DSPs) by breaking the standard of serial execution and accomplishing more per clock cycle. Controlling inputs and outputs (I/O) at the hardware level gives faster response time and particular functionality to match application requirements closely .
- Time to market– FPGA technology provides flexibility and rapid prototyping features in the face of increased time-to-market concerns. It enables you to test an idea or concept and verify it in hardware. The incremental changes are implemented and are iterated on an FPGA design within hours. Commercial off-the-shelf (COTS) hardware is present with different types of I/O preconnected to a user-programmable FPGA chip.
- Cost– The non-recurring engineering (NRE) expenditure of custom ASIC design goes beyond that of FPGA-based hardware solutions. As system requirements often changes with time, the cost of making an incremental alteration to FPGA designs is negligible compared to the expensive respinning an ASIC.
- Reliability– Processor-based systems involves various layers of abstraction to help schedule tasks and distribute resources among multiple processes. The driver layer manages hardware resources and the OS controls both memory and processor bandwidth. FPGAs minimizes reliability concerns with real parallel execution and hardware dedicated to every task.
- Long-term maintenance– FPGA chips are field-upgradable and being reconfigurable, they can keep up with future enhancements that are deemed necessary. As a product or system matures, you can make functional alterations without spending time redesigning hardware or modifying the board layout.
What is the difference between an ASIC and an FPGA?
ASIC and FPGAs have varying value propositions and it must be determined carefully before preferring either over the other. Data abounds that analyzes the two technologies. FPGAs easily push the 500 MHz performance barrier and features such as embedded processors, DSP blocks, clocking, and high-speed serial at ever lower price points, FPGAs are a compelling option for almost any type of design. They can be adjusted postfork
FPGAs are better because they produce the high hashrate at a fraction of the electricity cost. When compared to ASICs, FPGAs are better as they offer flexibility. This means once you own a FPGA card you can configure it as required to mine different cryptocurrencies.
Supposedly, if the prices of FPGA cards drop and with options available such as plug-and-play solutions, one can bet that FPGA will become more popular instantaneously. Also if there were decent entry-level FPGA cards at $300 to $500, lots of GPU miners would be ditching their equipment overnight.
Unless something with more advanced feature comes along, the share of FPGA miners is bound to increase in the next couple of years.